1. Field of the Invention
The present invention relates to a signal transfer technique and particularly relates to a technique effective to be applied to a high rate data transfer circuit method.
2. Description of the Related Art
According to the study of the inventor of the present invention, signal transfer related techniques are exemplified by those described in Japanese Patent Application Laid-Open Nos. 6-78003, 2000-244586, 7-44473, 2000-49575, and 10-327202 and that described in ISSCC 2000/SESSION 24/DRAM/PAPER WP 24.6.
Japanese Patent Application Laid-Open No. 6-78003 discloses a technique for providing a high rate data transfer method capable of transferring a large volume of data at one clock by converting digital data to analog data, i.e., to voltage data and then transmitting the converted voltage data.
Japanese Patent Application Laid-Open No. 2000-244586 discloses a data transmission system including a transmitter 100 for transmitting information to be transmitted and a reference signal referred to so as to demodulate the information, and a receiver 200 for receiving the information and the reference signal, in which the reference signal is subjected to channel- or time-division multiplexing and then transmitted.
Japanese Patent Application Laid-Open No. 7-44473 discloses a technique as follows. On a transmission side, each output driving circuit drives a corresponding signal line in accordance with an inputted signal, and a reference voltage generation circuit generates a reference voltage having a predetermined voltage relationship with a signal voltage from each output driving circuit and outputs the generated reference voltage to one signal line. On a receiving side, each voltage comparator compares the reference voltage from the one signal line with the signal voltage from the signal line connected to the corresponding output driving circuit, whereby the signal inputted into the corresponding output driving circuit is reproduced.
Japanese Patent Application Laid-Open No. 2000-49575 discloses an interface circuit including a clock wiring 101 for transmitting a clock signal from a master 10 to a slave 20, and a data wiring 102 for transmitting a data signal, in which the slave includes an averaging circuit 21 for generating an average voltage value Vref from an internal clock, and an input buffer 22 for comparing the inputted data signal propagated from the data wiring 102 with the average voltage value Vref and then outputting internal data 24.
Japanese Patent Application Laid-Open No. 10-327202 discloses a technique including a digital input terminal for individually inputting a data signal and a clock signal outputted in parallel from a digital output terminal of a digital broadcasting receiver, an averaging circuit for outputting a signal of a level obtained by averaging said inputted clock signal, and a first comparator for comparing the level of the inputted data signal with the output of this averaging circuit as a reference level, in which a data signal subjected to waveform shaping is fetched from this first comparator.
ISSCC 2000/SESSION 24/DRAM/PAPER WP 24.6 discloses a technique in which a capacitance is provided on data lines DataBus/DataBus# and the pair lines of a data line DataBus and a data line DataBus# are used as the data lines.